Pipeline CPU Simulator

Overview

Educational simulator that makes the classic 5-stage CPU pipeline tangible. Step through instructions one cycle at a time and watch them flow through fetch / decode / execute / memory / writeback — with hazards, forwarding, and stalls drawn directly onto the diagram. Built for computer-architecture students who learned the theory in lecture and need to see it move.

React + TypeScript single-page app, Vite-built and shipped to GitHub Pages. The pipeline state is fully observable: every register, every forwarding bypass, every stall bubble is visible at every cycle, so you can pause on any instruction and read off exactly what the hardware is doing.

Highlights

• ▸Cycle-accurate visualization of a 5-stage MIPS-style pipeline
• ▸Step-through execution: pause, advance, inspect any cycle
• ▸Hazard detection visualized — data, structural, control
• ▸Forwarding and stall logic drawn on the pipeline diagram
• ▸Register file and memory state live-updated each cycle
• ▸Loadable instruction sequences for classic teaching examples